In recent years, the submicron feature and the formation of the multi-layers of devices or wirings have been advanced with the high integration of a semiconductor device. While the submicron patterns of wirings have been formed by a thin film forming technology and a lithography technology, it is essentially necessary, upon formation of the multi-layers, to planarize a surface for the purpose of forming the submicron patterns with good accuracy. For instance, the submicron feature of a gate electrode greatly depends on the performance of the exposure device of the lithography technology. However, as for the submicron feature of a device isolation area and the reduction of distance from the gate electrode, the planarization technology of a substrate according to a Shallow Trench Isolation (refer it to as to STI, hereinafter) technology as well as a lithography technology also attracts attention.
As for the device isolation technology of LSI, an LOCOS isolation technology by a thermal oxide film has been hitherto employed. In the LOCOS, since an Si3N4 film is used as a mask to thermally oxidize an Si substrate itself, there exist great advantages that a process is simple and problems due to the device stress of the oxide film are rarely generated and the quality of the produced oxide film is good. Therefore, also in an LSI process in which a technological innovation is ardently carried out, an improvement is continuously performed in to the LOCOS isolation technology and the improved LOCOS isolation technology has been continuously used. However, as the generation of 0.25 μm occupies the main current, the LOCOS begins to arise a limitation from the viewpoint of submicron feature.
More specifically explained, a device isolation pitch is undesirably widened more by the approach of, what is called a bird's peak than the width of an opening of the Si3N4 film as the mask due to the bird's peak in which an oxidation reaction is spread in a transverse direction upon thermal oxidation. In order to suppress the bird's peak, a method for deleting a pad oxide film located just below the Si3N4 film may be effectively used, however, stress on the Si substrate by the Si3N4 film inconveniently causes the defect of crystal to be generated.
As described above, when the LOCOS is viewed from all-round aspects, the bird's peak becomes fatal so that it must be said that the submicron feature of the LOCOS is very difficult. Thus, as the device isolation technology, the STI is paid attention to in place of the LOCOS. According to the STI, since trenches are etched to fill insulating materials therein, there exists less conversion difference from a design dimension, and accordingly, the STI is suitable for the submicron manufacturing in principle. Further, since a surface planarizing operation is carried out by any method as described below after the insulating materials are filled in the trenches, the STI is advantageous in view of flatness required for highly accurate lithography.
The above described planarization technology is employed not only for the device isolation, but also for planarizing insulating films between wiring layers. Therefore, under these circumstances, a semiconductor device of next generation may not be established without the planarization technology.
As described above, the planarization technology essentially needs to be applied to a device of new generation. However, in recent years, a CMP (chemical mechanical polishing) technology has been ordinarily employed. An example in which the CMP technology is applied to the device isolation technology is shown in FIG. 10.
FIG. 10 shows a state in which trenches 102 are formed on a silicon substrates 101 and a filled insulating film 104 is filled therein by a CVD method. An Si3N4 film 103 is used as a CMP stopper layer to polish the filled insulating film 104 by employing a polishing material including silica as a main component from the state shown in FIG. 10.
The filled insulating film 104 used in this case is ordinarily formed by the plasma CVD method. However, according to the feature of the plasma CVD method, the film thickness t2 of the outer peripheral part of a wafer is apt to be inevitably larger than the film thickness t1 of the central part of the wafer (see FIG. 10).
In case that the CMP polishing is carried out from this state, when CMP polishing conditions are set on the basis of the film thickness of the central part of the wafer, the filled insulating film 104 on the Si3N4 film serving as the CMP stopper layer will not be polished and remain in the peripheral part of the wafer as shown in FIG. 11.
While this state is maintained, when the Si3N4 film as the stopper layer is to be removed by a wet etching method using hot phosphoric acid or an isotropic chemical dry etching method in a next step, the filled insulating film 104 remaining in the peripheral part of the wafer becomes a mask so that the film cannot be clearly removed. As a result, a desired processed form cannot be obtained in the peripheral part of the wafer so that the semiconductor device is inferior in view of characteristics, which causes a yield to be deteriorated.
For avoiding the above described adverse influences, when the filled insulating film 104 on the Si3N4 film 103 in the outer peripheral part of the wafer is to be polished so that the filled insulating film 104 is not left, the filled insulating film 104 in the trench 102 at the central part of the wafer is excessively polished next time. Thus, as shown in FIG. 12, the thickness of the filled insulating film 104 in the trench 102 at the central part of the wafer is different from that in the outer peripheral part.
At this time, there is not generated a problem in removing the Si3N4 film 103 as the stopper layer in a next step, however, since the film thickness of the filled insulating film 104 in the trench 102 is different between that of the central part of the wafer and that of the outer peripheral part of the wafer, a device isolation feature is consequently different in the surface of the wafer. Therefore, the desired characteristics of the semiconductor device cannot be obtained to cause a yield to be deteriorated.
Under these circumstances, a CMP planarization technology in which the processed film irrespective of the thickness of the processed film in the wafer is examined, however, desired results cannot be presently obtained.